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authorSagar Ghuge <[email protected]>2020-01-14 16:12:31 -0800
committerMarge Bot <[email protected]>2020-01-27 19:48:11 +0000
commita27542c5ddec8dd6a64a9c236cf6bea1db1b9e48 (patch)
tree9f01d45697ff8ebc58bc1dd65d4edc167d4dd2d9 /src/intel/genxml/gen75.xml
parent480cf7d9bf09086b246532e3612c61c8e2ea59da (diff)
intel/compiler: Clear accumulator register before EOT
v2: (Francisco Jerez) - Drop vec4 changes. - Handle explicit acc0 operand and implicit one. - Make sure instruction is SIMD16, prediction is off and default mask control set to true. v3: (Francisco Jerez) - Clear accumulator only when it's written. - Use BRW_MASK_DISABLE instead of true. - Use correct width for brw_acc_reg(). - Fix last_inst_offset. v4: (Francisco Jerez) - Don't check for last instruction for accummulator write. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3376> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3376>
Diffstat (limited to 'src/intel/genxml/gen75.xml')
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