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authorChris Wilson <[email protected]>2018-05-05 19:36:25 +0100
committerChris Wilson <[email protected]>2018-05-07 11:34:13 +0100
commitcf440d85db6d0ec3d2d5467cfa3d0462e4267261 (patch)
tree879846328f02248a36682c5bce13bb38b9347e54 /src/intel/genxml/gen5.xml
parentcd5319a64fb1a9b080521a03e08202e48aca448e (diff)
intel/genxml: Fix a few invalid field widths
A couple of typos found by inspecting field.end - field.start, revealed a few wide integers declared as bool and some that ended before they started. Cc: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/intel/genxml/gen5.xml')
-rw-r--r--src/intel/genxml/gen5.xml12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index 5c93ecdda30..5bb5a2c3312 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -1086,12 +1086,12 @@ i
<field name="CLIP Unit URB Reallocation Request" start="10" end="10" type="bool"/>
<field name="GS Unit URB Reallocation Request" start="9" end="9" type="bool"/>
<field name="VS Unit URB Reallocation Request" start="8" end="8" type="bool"/>
- <field name="CLIP Fence" start="52" end="61" type="bool"/>
- <field name="GS Fence" start="42" end="51" type="bool"/>
- <field name="VS Fence" start="32" end="41" type="bool"/>
- <field name="CS Fence" start="84" end="94" type="bool"/>
- <field name="VFE Fence" start="74" end="83" type="bool"/>
- <field name="SF Fence" start="64" end="73" type="bool"/>
+ <field name="CLIP Fence" start="52" end="61" type="uint"/>
+ <field name="GS Fence" start="42" end="51" type="uint"/>
+ <field name="VS Fence" start="32" end="41" type="uint"/>
+ <field name="CS Fence" start="84" end="94" type="uint"/>
+ <field name="VFE Fence" start="74" end="83" type="uint"/>
+ <field name="SF Fence" start="64" end="73" type="uint"/>
</instruction>
<instruction name="XY_COLOR_BLT" bias="2" length="6">