diff options
| author | Lionel Landwerlin <[email protected]> | 2020-02-02 14:25:16 +0100 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2020-05-20 14:02:27 +0300 |
| commit | cc13bfbd05934f4053b633627f5bd2ef1108537b (patch) | |
| tree | f7e8965ba3d8377ee66ed79bb8edac6763246cb8 /src/intel/genxml/gen12.xml | |
| parent | 34a0ce58c7f85ea3ec3f1026469ce06602f38a5b (diff) | |
intel/genxml: add PIPE_CONTROL command cache invalidate bit
This new bit invalidates the cache/prefetch of commands in the command
streamer. This will be useful for self modifying batches.
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
Diffstat (limited to 'src/intel/genxml/gen12.xml')
| -rw-r--r-- | src/intel/genxml/gen12.xml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index f5ccb182681..b8bada119c2 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -6413,6 +6413,7 @@ </field> <field name="Flush LLC" start="58" end="58" type="bool"/> <field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/> + <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool"/> <field name="Address" start="66" end="111" type="address"/> <field name="Immediate Data" start="128" end="191" type="uint"/> </instruction> |