diff options
| author | Jason Ekstrand <[email protected]> | 2017-03-29 15:16:15 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2017-04-04 18:33:35 -0700 |
| commit | 3503b2714b98684a2ceba5f4fd9a5bfbfbcaad38 (patch) | |
| tree | e408ab3e83e2bcc7ddc8a0135a70f205388e50d5 /src/intel/compiler | |
| parent | c5bf7cb52942cb7df9f5d73746ffbf3c102d12cc (diff) | |
i965/fs: Always provide a default LOD of 0 for TXS and TXL
We already provide a default LOD for textureQueryLevels and texture() on
non-fragment stages. However, there are more cases where one is needed
such as textureSize(gsampler2DMS*) in SPIR-V. Instead of trying to list
out all of the cases one at a time, just provide the default for all TXS
and TXL operations. This fixes a shader validation error in the new
Sascha deferredmultisampling demo which uses textureSize(gsampler2DMS).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100391
Reviewed-by: Anuj Phogat <[email protected]>
Cc: "13.0 17.0" <[email protected]>
Diffstat (limited to 'src/intel/compiler')
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index bc1ccfba3d2..23cd4b73f07 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4380,15 +4380,6 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr) srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(instr->coord_components); srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(lod_components); - if (instr->op == nir_texop_query_levels || - (instr->op == nir_texop_tex && stage != MESA_SHADER_FRAGMENT)) { - /* textureQueryLevels() and texture() are implemented in terms of TXS - * and TXL respectively, so we need to pass a valid LOD argument. - */ - assert(srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE); - srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u); - } - enum opcode opcode; switch (instr->op) { case nir_texop_tex: @@ -4455,6 +4446,15 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr) unreachable("unknown texture opcode"); } + /* TXS and TXL require a LOD but not everything we implement using those + * two opcodes provides one. Provide a default LOD of 0. + */ + if ((opcode == SHADER_OPCODE_TXS_LOGICAL || + opcode == SHADER_OPCODE_TXL_LOGICAL) && + srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE) { + srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u); + } + if (instr->op == nir_texop_tg4) { if (instr->component == 1 && key_tex->gather_channel_quirk_mask & (1 << texture)) { |