diff options
| author | Jason Ekstrand <[email protected]> | 2017-11-02 18:30:04 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2017-11-07 10:41:24 -0800 |
| commit | 9bb34892bf99a6f2285f792519f51cefe5c219ee (patch) | |
| tree | f7f930ea9105ca3aaa4d767fbc47ba81ffe15315 /src/intel/compiler | |
| parent | 1cb210f4bc412a9c1fef12e05ea9d9fe8995f4d5 (diff) | |
intel/fs/nir: Setup immediates based on type in i2b and f2b
Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
Diffstat (limited to 'src/intel/compiler')
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 2f47b0253b2..99e652a4a0c 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1125,12 +1125,13 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) if (instr->op == nir_op_f2b) { zero = vgrf(glsl_type::double_type); tmp = vgrf(glsl_type::double_type); + bld.MOV(zero, setup_imm_df(bld, 0.0)); } else { zero = vgrf(glsl_type::int64_t_type); tmp = vgrf(glsl_type::int64_t_type); + bld.MOV(zero, brw_imm_q(0)); } - bld.MOV(zero, setup_imm_df(bld, 0.0)); /* A SIMD16 execution needs to be split in two instructions, so use * a vgrf instead of the flag register as dst so instruction splitting * works |