diff options
| author | Lionel Landwerlin <[email protected]> | 2017-06-20 11:06:24 +0100 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2017-06-20 23:26:42 +0100 |
| commit | 030abc61091a38596427aa04022066719be9add5 (patch) | |
| tree | 31bcc61d00bf788ffa04a03aacd8a2451427c50e /src/intel/compiler | |
| parent | b3b61211157ab934f1898d3519e7288c1fd89d80 (diff) | |
intel: compiler/i965: fix is_broxton checks
In 5f2fe9302c is_geminilake was introduced for the differenciate
broxton from geminilake. Unfortunately I failed as verifying that
is_broxton is throughout the code base to mean Gen9lp.
Fixes: 5f2fe9302c ("intel: common: add flag to identify platforms by name")
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler')
| -rw-r--r-- | src/intel/compiler/brw_fs.cpp | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 4 | ||||
| -rw-r--r-- | src/intel/compiler/brw_vec4.cpp | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 90a650add07..43b6e342043 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -3348,7 +3348,7 @@ fs_visitor::lower_integer_multiplication() * operation directly, but CHV/BXT cannot. */ if (devinfo->gen >= 8 && - !devinfo->is_cherryview && !devinfo->is_broxton) + !devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo)) continue; if (inst->src[1].file == IMM && diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 876b1030ec0..a9dce42c38d 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -639,7 +639,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) */ if (nir_dest_bit_size(instr->dest.dest) == 64 && nir_src_bit_size(instr->src[0].src) == 32 && - (devinfo->is_cherryview || devinfo->is_broxton)) { + (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) { fs_reg tmp = bld.vgrf(result.type, 1); tmp = subscript(tmp, op[0].type, 0); inst = bld.MOV(tmp, op[0]); @@ -3748,7 +3748,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr (instr->num_components - 1) * type_sz(dest.type); bool supports_64bit_indirects = - !devinfo->is_cherryview && !devinfo->is_broxton; + !devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo); if (type_sz(dest.type) != 8 || supports_64bit_indirects) { for (unsigned j = 0; j < instr->num_components; j++) { diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index b443effca9a..3de7d931dde 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -985,7 +985,7 @@ vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst) * affected, at least by the 64b restriction, since DepCtrl with double * precision instructions seems to produce GPU hangs in some cases. */ - if (devinfo->gen == 8 || devinfo->is_broxton) { + if (devinfo->gen == 8 || gen_device_info_is_9lp(devinfo)) { if (inst->opcode == BRW_OPCODE_MUL && IS_DWORD(inst->src[0]) && IS_DWORD(inst->src[1])) |