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authorSagar Ghuge <[email protected]>2019-03-27 17:07:01 -0700
committerMatt Turner <[email protected]>2019-05-07 14:33:48 -0700
commit6c83a68ebc381b46a4226c0ebd060cbc0d3f8056 (patch)
treebb478c3599e750f7eb6b065c6dd371da0c52903a /src/intel/compiler
parent9db616e8a2e86354a3ba9851d84911f7cc623f9b (diff)
intel/disasm: Disassemble JIP offset for while
Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel/compiler')
-rw-r--r--src/intel/compiler/brw_disasm.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 04efa965cef..e1cc0f4925f 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1661,7 +1661,8 @@ brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
format(file, "Pop: %"PRIu64, brw_inst_gen4_pop_count(devinfo, inst));
} else if (devinfo->gen < 6 && (opcode == BRW_OPCODE_IF ||
opcode == BRW_OPCODE_IFF ||
- opcode == BRW_OPCODE_HALT)) {
+ opcode == BRW_OPCODE_HALT ||
+ opcode == BRW_OPCODE_WHILE)) {
pad(file, 16);
format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst));
} else if (devinfo->gen < 6 && opcode == BRW_OPCODE_ENDIF) {