diff options
| author | Jason Ekstrand <[email protected]> | 2018-05-18 20:04:12 -0700 |
|---|---|---|
| committer | Dylan Baker <[email protected]> | 2018-05-30 16:56:47 -0700 |
| commit | 14689dccbfaf11e5b83aeb971155c77cbc486477 (patch) | |
| tree | 4d88ad709dc67c3c0b6f00abfeb1ecab632ac228 /src/intel/compiler | |
| parent | 66604a75181f52d1fc64d09757f364f200ef566b (diff) | |
intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0
Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..."
Reviewed-by: Jose Maria Casanova Crespo <[email protected]>
(cherry picked from commit 417b9e5770436008a7f00cfaffe9ddf4c5a13502)
Diffstat (limited to 'src/intel/compiler')
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index ee5a048bcaa..6d81c636f27 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -3713,6 +3713,7 @@ brw_rounding_mode(struct brw_codegen *p, if (bits != BRW_CR0_RND_MODE_MASK) { brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0), brw_imm_ud(~BRW_CR0_RND_MODE_MASK)); + brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1); /* From the Skylake PRM, Volume 7, page 760: * "Implementation Restriction on Register Access: When the control @@ -3727,6 +3728,7 @@ brw_rounding_mode(struct brw_codegen *p, if (bits) { brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0), brw_imm_ud(bits)); + brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1); brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH); } } |