diff options
| author | Boris Brezillon <[email protected]> | 2020-05-05 09:13:20 +0200 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-06-03 07:39:52 +0000 |
| commit | 345b5847b42bc1889d8665ebd129913550da4352 (patch) | |
| tree | d2f3e4a7b13ec1d3493fa7c5fb49e11969f52f81 /src/intel/compiler | |
| parent | 94438a64bf7e5cd37c56e954156d59e404d76f55 (diff) | |
nir: Replace the scoped_memory barrier by a scoped_barrier
SPIRV OpControlBarrier can have both a memory and a control barrier
which some hardware can handle with a single instruction. Let's
turn the scoped_memory_barrier into a scoped barrier which can embed
both barrier types. Note that control-only or memory-only barriers can
be supported through this new intrinsic by passing NIR_SCOPE_NONE to the
unused barrier type.
Signed-off-by: Boris Brezillon <[email protected]>
Suggested-by: Caio Marcelo de Oliveira Filho <[email protected]>
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4900>
Diffstat (limited to 'src/intel/compiler')
| -rw-r--r-- | src/intel/compiler/brw_compiler.c | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 5 | ||||
| -rw-r--r-- | src/intel/compiler/brw_vec4_nir.cpp | 6 |
3 files changed, 8 insertions, 5 deletions
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 0c28b81e912..c26b6eb3bbc 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -48,7 +48,7 @@ .use_interpolated_input_intrinsics = true, \ .vertex_id_zero_based = true, \ .lower_base_vertex = true, \ - .use_scoped_memory_barrier = true, \ + .use_scoped_barrier = true, \ .support_8bit_alu = true, \ .support_16bit_alu = true diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 37c1d2f4cc9..37f03507bb0 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4225,7 +4225,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr break; } - case nir_intrinsic_scoped_memory_barrier: + case nir_intrinsic_scoped_barrier: + assert(nir_intrinsic_execution_scope(instr) == NIR_SCOPE_NONE); case nir_intrinsic_group_memory_barrier: case nir_intrinsic_memory_barrier_shared: case nir_intrinsic_memory_barrier_buffer: @@ -4239,7 +4240,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr SHADER_OPCODE_INTERLOCK : SHADER_OPCODE_MEMORY_FENCE; switch (instr->intrinsic) { - case nir_intrinsic_scoped_memory_barrier: { + case nir_intrinsic_scoped_barrier: { nir_variable_mode modes = nir_intrinsic_memory_modes(instr); l3_fence = modes & (nir_var_shader_out | nir_var_mem_ssbo | diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 76446adcf54..13a5d2f4fa9 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -700,8 +700,10 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) break; } - case nir_intrinsic_memory_barrier: - case nir_intrinsic_scoped_memory_barrier: { + case nir_intrinsic_scoped_barrier: + assert(nir_intrinsic_execution_scope(instr) == NIR_SCOPE_NONE); + /* Fall through. */ + case nir_intrinsic_memory_barrier: { const vec4_builder bld = vec4_builder(this).at_end().annotate(current_annotation, base_ir); const dst_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD); |