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authorSamuel Iglesias Gonsálvez <[email protected]>2017-04-26 10:12:03 +0200
committerSamuel Iglesias Gonsálvez <[email protected]>2017-05-03 15:32:39 +0200
commit7f728bce811fc283e672e3a07b008bb7b52de35e (patch)
treefa51548f6b5f286c12acde54b9631d596278cddf /src/intel/compiler/intel_asm_annotation.c
parent3bf3f9866c1387872521242921bb00c7fb7c2834 (diff)
i965/vec4: fix vertical stride to avoid breaking region parameter rule
From IVB PRM, vol4, part3, "General Restrictions on Regioning Parameters": "If ExecSize = Width and HorzStride ≠ 0, VertStride must be set to Width * HorzStride." In next patch, we are going to modify the region parameter for uniforms and vgrf. For uniforms that are the source of DF align1 instructions, they will have <0, 4, 1> regioning and the execsize for those instructions will be 4, so they will break the regioning rule. This will be the same for VGRF sources where we use the vstride == 0 exploit. As we know we are not going to cross the GRF boundary with that execsize and parameters (not even with the exploit), we just fix the vstride here. v2: - Move is_align1_df() (Curro) - Refactor exec_size == width calculation (Curro) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Cc: "17.1" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
Diffstat (limited to 'src/intel/compiler/intel_asm_annotation.c')
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