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| author | Iago Toral Quiroga <[email protected]> | 2017-10-09 14:17:43 +0200 |
|---|---|---|
| committer | Iago Toral Quiroga <[email protected]> | 2017-10-10 08:59:54 +0200 |
| commit | 5ec21eb1a0c9fa08978784e58456fdd212aab4d7 (patch) | |
| tree | 43b11a726fc45d97f35f507e8987fc798479bc03 /src/intel/compiler/brw_vue_map.c | |
| parent | 63e6db18c5cdec50688d604a43ddaf86a2238f76 (diff) | |
i965/tes: account for the fact that dvec3/4 inputs take two slots
When computing the total size of the URB for tessellation evaluation
inputs we were not accounting for this, and instead we were always
assuming that each input would take a single vec4 slot, which could
lead to computing a smaller read size than required. Specifically, this
is a problem when the last input is a dvec3/4 such that its XY components
are stored in the the second half of a payload register (which can happen
if the offset for the input in the URB is not 64-bit aligned because
there are 32-bit inputs mixed in) and the ZW components in the
first half of the next, as in this case we would fail to account for the
extra slot required for the ZW components.
Fixes (requires another fix in CTS currently in review):
KHR-GL45.enhanced_layouts.varying_locations
KHR-GL45.enhanced_layouts.varying_array_locations
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vue_map.c')
0 files changed, 0 insertions, 0 deletions