diff options
| author | Anuj Phogat <[email protected]> | 2016-01-05 08:41:39 -0800 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2017-06-09 16:02:59 -0700 |
| commit | f9e31a26d4cf075e236e92aea63bb69eb9fad533 (patch) | |
| tree | 4dc2ec84e9a66435198746ea6b2e0c431068f78d /src/intel/compiler/brw_vec4_tcs.cpp | |
| parent | b76659997ebb08e69430bfd5eafbe2af5d494a8f (diff) | |
i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3
v1: By Ben Widawsky <[email protected]>
v2: v1 had an assert only for VS. Add the restriction for GS, HS and
DS as well and make sure the allocated sizes are not multiple of 3.
v3: Move the entry_size checks in to compiler code (Ken)
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vec4_tcs.cpp')
| -rw-r--r-- | src/intel/compiler/brw_vec4_tcs.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 96597b8f2ad..c4d9f89a91b 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -441,6 +441,13 @@ brw_compile_tcs(const struct brw_compiler *compiler, /* URB entry sizes are stored as a multiple of 64 bytes. */ vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64; + /* On Cannonlake software shall not program an allocation size that + * specifies a size that is a multiple of 3 64B (512-bit) cachelines. + */ + if (devinfo->gen == 10 && + vue_prog_data->urb_entry_size % 3 == 0) + vue_prog_data->urb_entry_size++; + /* HS does not use the usual payload pushing from URB to GRFs, * because we don't have enough registers for a full-size payload, and * the hardware is broken on Haswell anyway. |