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authorLionel Landwerlin <[email protected]>2017-08-03 14:50:35 +0100
committerLionel Landwerlin <[email protected]>2017-11-01 13:19:20 +0000
commit68e1853ea3a6feabf14cbe42e8e003647fdc82f3 (patch)
tree1c17d010671fa5fae0df9aed93945a0799dfa6a8 /src/intel/compiler/brw_vec4_reg_allocate.cpp
parentf5e5ca1e210c2e0f505ea154ca553275157dda73 (diff)
intel: decoder: don't read qword outside instruction/struct limit
We used to print invalid data when the last field was being clamped to 32bits due to Dword Length of the whole instruction. Here is an example where the decoder read part of the next instruction instead of stopping at the 32bit limit: 0x000ce0b4: 0x10000002: MI_STORE_DATA_IMM 0x000ce0b4: 0x10000002 : Dword 0 DWord Length: 2 Store Qword: 0 Use Global GTT: false 0x000ce0b8: 0x00045010 : Dword 1 Core Mode Enable: 0 Address: 0x00045010 0x000ce0bc: 0x00000000 : Dword 2 0x000ce0c0: 0x00000000 : Dword 3 Immediate Data: 8791026489807077376 With this change we have the proper value : 0x000ce0b4: 0x10000002: MI_STORE_DATA_IMM (4 Dwords) 0x000ce0b4: 0x10000002 : Dword 0 DWord Length: 2 Store Qword: 0 Use Global GTT: false 0x000ce0b8: 0x00045010 : Dword 1 Core Mode Enable: 0 Address: 0x00045010 0x000ce0bc: 0x00000000 : Dword 2 0x000ce0c0: 0x00000000 : Dword 3 Immediate Data: 0 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vec4_reg_allocate.cpp')
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