diff options
author | Jason Ekstrand <[email protected]> | 2017-03-07 19:54:37 -0800 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2017-03-14 07:36:40 -0700 |
commit | 762a6333f21fd8606f69db6060027c4522d46678 (patch) | |
tree | f77c695fa16a5d869175773229d0195c22060c93 /src/intel/compiler/brw_vec4_nir.cpp | |
parent | 7107b321557e421e33fe92221133cf4a08eb7c6c (diff) |
nir: Rework conversion opcodes
The NIR story on conversion opcodes is a mess. We've had way too many
of them, naming is inconsistent, and which ones have explicit sizes was
sort-of random. This commit re-organizes things and makes them all
consistent:
- All non-bool conversion opcodes now have the explicit size in the
destination and are named <src_type>2<dst_type><size>.
- Integer <-> integer conversion opcodes now only come in i2i and u2u
forms (i2u and u2i have been removed) since the only difference
between the different integer conversions is whether or not they
sign-extend when up-converting.
- Boolean conversion opcodes all have the explicit size on the bool and
are named <src_type>2<dst_type>.
Making things consistent also allows nir_type_conversion_op to be moved
to nir_opcodes.c and auto-generated using mako. This will make adding
int8, int16, and float16 versions much easier when the time comes.
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vec4_nir.cpp')
-rw-r--r-- | src/intel/compiler/brw_vec4_nir.cpp | 67 |
1 files changed, 29 insertions, 38 deletions
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index ca2e5dd05eb..23842653997 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -1287,32 +1287,24 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_vec4: unreachable("not reached: should be handled by lower_vec_to_movs()"); - case nir_op_i2f: - case nir_op_u2f: + case nir_op_i2f32: + case nir_op_u2f32: inst = emit(MOV(dst, op[0])); inst->saturate = instr->dest.saturate; break; - case nir_op_f2i: - case nir_op_f2u: - inst = emit(MOV(dst, op[0])); - break; - - case nir_op_d2f: - emit_conversion_from_double(dst, op[0], instr->dest.saturate); - break; - - case nir_op_f2d: - emit_conversion_to_double(dst, op[0], instr->dest.saturate); - break; - - case nir_op_d2i: - case nir_op_d2u: - emit_conversion_from_double(dst, op[0], instr->dest.saturate); + case nir_op_f2f32: + case nir_op_f2i32: + case nir_op_f2u32: + if (nir_src_bit_size(instr->src[0].src) == 64) + emit_conversion_from_double(dst, op[0], instr->dest.saturate); + else + inst = emit(MOV(dst, op[0])); break; - case nir_op_i2d: - case nir_op_u2d: + case nir_op_f2f64: + case nir_op_i2f64: + case nir_op_u2f64: emit_conversion_to_double(dst, op[0], instr->dest.saturate); break; @@ -1681,26 +1673,25 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_f2b: - emit(CMP(dst, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ)); - break; - - case nir_op_d2b: { - /* We use a MOV with conditional_mod to check if the provided value is - * 0.0. We want this to flush denormalized numbers to zero, so we set a - * source modifier on the source operand to trigger this, as source - * modifiers don't affect the result of the testing against 0.0. - */ - src_reg value = op[0]; - value.abs = true; - vec4_instruction *inst = emit(MOV(dst_null_df(), value)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; + if (nir_src_bit_size(instr->src[0].src) == 64) { + /* We use a MOV with conditional_mod to check if the provided value is + * 0.0. We want this to flush denormalized numbers to zero, so we set a + * source modifier on the source operand to trigger this, as source + * modifiers don't affect the result of the testing against 0.0. + */ + src_reg value = op[0]; + value.abs = true; + vec4_instruction *inst = emit(MOV(dst_null_df(), value)); + inst->conditional_mod = BRW_CONDITIONAL_NZ; - src_reg one = src_reg(this, glsl_type::ivec4_type); - emit(MOV(dst_reg(one), brw_imm_d(~0))); - inst = emit(BRW_OPCODE_SEL, dst, one, brw_imm_d(0)); - inst->predicate = BRW_PREDICATE_NORMAL; + src_reg one = src_reg(this, glsl_type::ivec4_type); + emit(MOV(dst_reg(one), brw_imm_d(~0))); + inst = emit(BRW_OPCODE_SEL, dst, one, brw_imm_d(0)); + inst->predicate = BRW_PREDICATE_NORMAL; + } else { + emit(CMP(dst, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ)); + } break; - } case nir_op_i2b: emit(CMP(dst, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ)); |