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authorSamuel Iglesias Gonsálvez <[email protected]>2017-10-09 12:25:39 +0200
committerSamuel Iglesias Gonsálvez <[email protected]>2017-10-20 08:29:53 +0200
commit9e515cf38138bc0e7e884f893335ed486eac5741 (patch)
tree8499f79cd1ec05b6681794b0dee567b31c96c0e9 /src/intel/compiler/brw_vec4_nir.cpp
parentc6d7d09bd0a77f1b6d0afbbbe1ecdb1600ecce8c (diff)
i965/vec4: remove setting default LOD in the backend
It is already done in NIR. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vec4_nir.cpp')
-rw-r--r--src/intel/compiler/brw_vec4_nir.cpp9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index 9200ffa0ed7..0a1caa9fad8 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -2228,15 +2228,6 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
}
}
- /* TXS and TXL require a LOD but not everything we implement using those
- * two opcodes provides one. Provide a default LOD of 0.
- */
- if ((instr->op == nir_texop_txs ||
- instr->op == nir_texop_txl) &&
- lod.file == BAD_FILE) {
- lod = brw_imm_ud(0u);
- }
-
if (instr->op == nir_texop_txf_ms ||
instr->op == nir_texop_samples_identical) {
assert(coord_type != NULL);