diff options
| author | Francisco Jerez <[email protected]> | 2017-12-12 12:05:02 -0800 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2018-03-02 11:28:56 -0800 |
| commit | cc0fc8b8ac608b036d260007a689eeeb8e815031 (patch) | |
| tree | aa6f8eb8154874a108154560992a7aa6946da791 /src/intel/compiler/brw_vec4_generator.cpp | |
| parent | 9ec3362e0ba293f20d08493753edeb29d13baadf (diff) | |
intel/ir: Allow representing additional flag subregisters in the IR.
This allows representing conditional mods and predicates on f1.0-f1.1
at the IR level by adding an extra bit to the flag_subreg
backend_instruction field.
Reviewed-by: Jordan Justen <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vec4_generator.cpp')
| -rw-r--r-- | src/intel/compiler/brw_vec4_generator.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index f5d6ad8e483..6fa6e35b24a 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -1517,7 +1517,7 @@ generate_code(struct brw_codegen *p, brw_set_default_predicate_control(p, inst->predicate); brw_set_default_predicate_inverse(p, inst->predicate_inverse); - brw_set_default_flag_reg(p, 0, inst->flag_subreg); + brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2); brw_set_default_saturate(p, inst->saturate); brw_set_default_mask_control(p, inst->force_writemask_all); brw_set_default_acc_write_control(p, inst->writes_accumulator); |