diff options
| author | Matt Turner <[email protected]> | 2017-06-14 16:20:41 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2018-02-28 11:15:47 -0800 |
| commit | 89fe5190a256ee0939061c4c264e9156256d16e8 (patch) | |
| tree | 01a231a3cd2109f134c285a6caa715eec95a6e2a /src/intel/compiler/brw_vec4_builder.h | |
| parent | 2134ea380033d5d1f3c5760b8bdb1da7aadd9842 (diff) | |
intel/compiler: Lower flrp32 on Gen11+
The LRP instruction is no more.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vec4_builder.h')
| -rw-r--r-- | src/intel/compiler/brw_vec4_builder.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_vec4_builder.h b/src/intel/compiler/brw_vec4_builder.h index 4c3efe8457b..5c880c19f52 100644 --- a/src/intel/compiler/brw_vec4_builder.h +++ b/src/intel/compiler/brw_vec4_builder.h @@ -501,7 +501,7 @@ namespace brw { LRP(const dst_reg &dst, const src_reg &x, const src_reg &y, const src_reg &a) const { - if (shader->devinfo->gen >= 6) { + if (shader->devinfo->gen >= 6 && shader->devinfo->gen <= 10) { /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so * we need to reorder the operands. */ |