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| author | Samuel Pitoiset <[email protected]> | 2018-11-08 11:16:45 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-11-08 11:20:03 +0100 |
| commit | c472ad82e48e139e03ed28a7a98481814260d08e (patch) | |
| tree | 78b80276779761af28d71efd4a1996414c602b49 /src/intel/compiler/brw_vec4.h | |
| parent | f425d9ee74ce81be3aa9dfefad572d40c5d42372 (diff) | |
radv: fix GPU hangs when loading depth/stencil clear values on SI/CIK
HTILE is supported on these chips, not sure how I missed that.
This restores using PFP_SYNC_ME when LOAD_CONTEXT_REG is not used.
Fixes: f425d9ee74 ("radv: use LOAD_CONTEXT_REG when loading fast clear values")
Signed-off-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vec4.h')
0 files changed, 0 insertions, 0 deletions