diff options
| author | Antia Puentes <[email protected]> | 2018-04-28 14:09:20 +0200 |
|---|---|---|
| committer | Antia Puentes <[email protected]> | 2018-05-02 11:23:34 +0200 |
| commit | 0cbf29fa5592b7feba6a307d597915cc07be828c (patch) | |
| tree | 6f7c343c7326b9ca9dedbc69cf1554d0f0da62ef /src/intel/compiler/brw_vec4.cpp | |
| parent | 6ba9088d9c692bfdafdf354ee96f662166582a79 (diff) | |
intel: emit is_indexed_draw in the same VE than gl_DrawID
The Vertex Elements are now:
* VE 1: <BaseVertex/firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <DrawID, is-indexed-draw, 0, 0>
VE1 is it kept as it was before, VE2 additionally contains the new
system value.
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vec4.cpp')
| -rw-r--r-- | src/intel/compiler/brw_vec4.cpp | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index e583c549204..898df90225f 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -2833,6 +2833,13 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, nr_attribute_slots++; } + /* gl_DrawID and IsIndexedDraw share its very own vec4 */ + if (shader->info.system_values_read & + (BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID) | + BITFIELD64_BIT(SYSTEM_VALUE_IS_INDEXED_DRAW))) { + nr_attribute_slots++; + } + if (shader->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX)) prog_data->uses_basevertex = true; @@ -2857,12 +2864,9 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID)) prog_data->uses_instanceid = true; - /* gl_DrawID has its very own vec4 */ if (shader->info.system_values_read & - BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID)) { - prog_data->uses_drawid = true; - nr_attribute_slots++; - } + BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID)) + prog_data->uses_drawid = true; /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in |