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authorKenneth Graunke <[email protected]>2017-04-22 15:02:08 -0700
committerKenneth Graunke <[email protected]>2017-04-24 10:53:49 -0700
commit6b10c37b9c3a73add73f444fe1aee73c9ec82c94 (patch)
tree078a9870ef6ec30b1d75fee71a6d83150a42655a /src/intel/compiler/brw_vec4.cpp
parent11db3d10bbab2fac0e7a1dfef08df72760b6badc (diff)
i965/vec4: Use reads_accumulator_implicitly(), not MACH checks.
Curro pointed out that I should not just check for MACH, but use the reads_accumulator_implicitly() helper, which would also prevent the same bug with MAC and SADA2 (if we ever decide to use them). Cc: [email protected] Reviewed-by: Francisco Jerez <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vec4.cpp')
-rw-r--r--src/intel/compiler/brw_vec4.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 4bb774bf10e..0909ddb5861 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -1071,11 +1071,11 @@ vec4_instruction::can_reswizzle(const struct gen_device_info *devinfo,
if (devinfo->gen == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW)
return false;
- /* Don't touch MACH - it uses the accumulator results from an earlier
- * MUL - so we'd need to reswizzle both. We don't do that, so just
- * avoid it entirely.
+ /* We can't swizzle implicit accumulator access. We'd have to
+ * reswizzle the producer of the accumulator value in addition
+ * to the consumer (i.e. both MUL and MACH). Just skip this.
*/
- if (opcode == BRW_OPCODE_MACH)
+ if (reads_accumulator_implicitly())
return false;
if (!can_do_writemask(devinfo) && dst_writemask != WRITEMASK_XYZW)