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| author | Caio Marcelo de Oliveira Filho <[email protected]> | 2020-05-21 01:56:54 -0700 |
|---|---|---|
| committer | Caio Marcelo de Oliveira Filho <[email protected]> | 2020-05-27 18:16:31 -0700 |
| commit | 90ec26a800ca7d24237b9df9b2549452f4aa9946 (patch) | |
| tree | 96d8b819beda1b1dc143c52d94601afe45bd4c8c /src/intel/compiler/brw_vec4.cpp | |
| parent | 9b8347c98842621a621746ec5718c95d297876c9 (diff) | |
intel/fs: Generate multiple CS SIMD variants for variable group size
This will make the GL drivers pick the right SIMD variant for a given
group size set during dispatch. The heuristic implemented in
brw_cs_simd_size_for_group_size() is the same as in brw_compile_cs().
The cs_prog_data::simd_size field was removed. The generated SIMD
sizes are marked in a bitmask, which is already used via
brw_cs_simd_size_for_group_size() by the drivers.
When in variable group size, it is OK if larger SIMD shader spill,
since we'd need it for the cases where the smaller one can't hold all
the invocations.
Reviewed-by: Jason Ekstrand <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
Diffstat (limited to 'src/intel/compiler/brw_vec4.cpp')
0 files changed, 0 insertions, 0 deletions