diff options
| author | Jason Ekstrand <[email protected]> | 2017-09-01 15:18:02 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2018-03-07 12:13:47 -0800 |
| commit | 8b4a5e641bc3cb9cf0cfe7d0487926127fc25de7 (patch) | |
| tree | 677f320e6c04883a55a4f2592549428154972423 /src/intel/compiler/brw_shader.cpp | |
| parent | 2292b20b2969c9e3e0494ccc55c6216f330762ae (diff) | |
intel/fs: Add support for subgroup quad operations
NIR has code to lower these away for us but we can do significantly
better in many cases with register regioning and SIMD4x2.
Acked-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_shader.cpp')
| -rw-r--r-- | src/intel/compiler/brw_shader.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index e822c100e9f..ffe8a7403da 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -334,6 +334,8 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) return "shuffle"; case SHADER_OPCODE_SEL_EXEC: return "sel_exec"; + case SHADER_OPCODE_QUAD_SWIZZLE: + return "quad_swizzle"; case SHADER_OPCODE_CLUSTER_BROADCAST: return "cluster_broadcast"; |