diff options
| author | Jason Ekstrand <[email protected]> | 2019-02-21 10:14:17 -0600 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2019-02-28 16:58:20 -0600 |
| commit | aeaba24fcb98839be73a59f6bb74a39523d79a3d (patch) | |
| tree | ed108ed75c232405b247442ca594758d236c70d9 /src/intel/compiler/brw_schedule_instructions.cpp | |
| parent | a04c73721591d4b8174f32e5d1fe5db2a5157ea4 (diff) | |
intel/compiler: Drop unused surface opcodes
The unused typed surface read/write support in the vec4 back-end has
been dropped and the fs back-end now uses SHADER_OPCODE_SEND for all
image and buffer ops. There's no reason to keep these opcodes around
anymore.
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_schedule_instructions.cpp')
| -rw-r--r-- | src/intel/compiler/brw_schedule_instructions.cpp | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index 861b2abfff2..4a516223cf9 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -368,8 +368,6 @@ schedule_node::set_latency_gen7(bool is_haswell) break; case SHADER_OPCODE_UNTYPED_ATOMIC: - case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT: - case SHADER_OPCODE_TYPED_ATOMIC: /* Test code: * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q }; * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all }; @@ -389,8 +387,6 @@ schedule_node::set_latency_gen7(bool is_haswell) case SHADER_OPCODE_UNTYPED_SURFACE_READ: case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: - case SHADER_OPCODE_TYPED_SURFACE_READ: - case SHADER_OPCODE_TYPED_SURFACE_WRITE: /* Test code: * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q }; * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all }; |