diff options
| author | Jason Ekstrand <[email protected]> | 2019-02-21 10:41:59 -0600 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2019-02-28 16:58:20 -0600 |
| commit | e8f863e7189076d7005c4586f1512d0f87afc1d8 (patch) | |
| tree | 3e53030eb9000bf0eaabf647ca6b55c82902de3c /src/intel/compiler/brw_schedule_instructions.cpp | |
| parent | 95ae400abcda4f692fd31c9132462d904f939ec3 (diff) | |
intel/compiler: Re-prefix non-logical surface opcodes with VEC4
The scalar back-end uses SHADER_OPCODE_SEND for all surface messages so
we no longer need the non-logical opcodes there. Prefix them VEC4 so
it's clear that they're only used by the vec4 back-end.
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_schedule_instructions.cpp')
| -rw-r--r-- | src/intel/compiler/brw_schedule_instructions.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index 1d5ee56bd4a..4fed1492ff7 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -367,13 +367,13 @@ schedule_node::set_latency_gen7(bool is_haswell) latency = 50; break; - case SHADER_OPCODE_UNTYPED_ATOMIC: + case VEC4_OPCODE_UNTYPED_ATOMIC: /* See GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP */ latency = 14000; break; - case SHADER_OPCODE_UNTYPED_SURFACE_READ: - case SHADER_OPCODE_UNTYPED_SURFACE_WRITE: + case VEC4_OPCODE_UNTYPED_SURFACE_READ: + case VEC4_OPCODE_UNTYPED_SURFACE_WRITE: /* See also GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ */ latency = is_haswell ? 300 : 600; break; |