diff options
author | Jason Ekstrand <[email protected]> | 2018-10-30 12:23:44 -0500 |
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committer | Jason Ekstrand <[email protected]> | 2019-01-29 18:43:55 +0000 |
commit | d2d3e0450119d8c52a3dd0dd89bfc9182a1cfce7 (patch) | |
tree | c4b526052607c474a7b7fa1e408ec2f48b3ab486 /src/intel/compiler/brw_schedule_instructions.cpp | |
parent | 7f1cf046cd1fb8a3af0e24b622179e4adb398764 (diff) |
intel/fs: Use SHADER_OPCODE_SEND for surface messages
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_schedule_instructions.cpp')
-rw-r--r-- | src/intel/compiler/brw_schedule_instructions.cpp | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index bc4c2dc5cdb..f453bb42574 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -416,6 +416,78 @@ schedule_node::set_latency_gen7(bool is_haswell) case SHADER_OPCODE_SEND: switch (inst->sfid) { + case GEN6_SFID_DATAPORT_RENDER_CACHE: + switch ((inst->desc >> 14) & 0x1f) { + case GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE: + case GEN7_DATAPORT_RC_TYPED_SURFACE_READ: + /* See also SHADER_OPCODE_TYPED_SURFACE_READ */ + assert(!is_haswell); + latency = 600; + break; + + case GEN7_DATAPORT_RC_TYPED_ATOMIC_OP: + /* See also SHADER_OPCODE_TYPED_ATOMIC */ + assert(!is_haswell); + latency = 14000; + break; + + default: + unreachable("Unknown render cache message"); + } + break; + + case GEN7_SFID_DATAPORT_DATA_CACHE: + switch ((inst->desc >> 14) & 0x1f) { + case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ: + case HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE: + /* We have no data for this but assume it's roughly the same as + * untyped surface read/write. + */ + latency = 300; + break; + + case GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ: + case GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE: + /* See also SHADER_OPCODE_UNTYPED_SURFACE_READ */ + assert(!is_haswell); + latency = 600; + break; + + case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP: + /* See also SHADER_OPCODE_UNTYPED_ATOMIC */ + assert(!is_haswell); + latency = 14000; + break; + + default: + unreachable("Unknown data cache message"); + } + break; + + case HSW_SFID_DATAPORT_DATA_CACHE_1: + switch ((inst->desc >> 14) & 0x1f) { + case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ: + case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE: + case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ: + case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE: + /* See also SHADER_OPCODE_UNTYPED_SURFACE_READ */ + latency = 300; + break; + + case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP: + case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2: + case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2: + case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP: + case GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP: + /* See also SHADER_OPCODE_UNTYPED_ATOMIC */ + latency = 14000; + break; + + default: + unreachable("Unknown data cache message"); + } + break; + default: unreachable("Unknown SFID"); } |