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author | Jason Ekstrand <[email protected]> | 2017-08-21 21:27:19 -0700 |
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committer | Jason Ekstrand <[email protected]> | 2017-11-07 10:37:52 -0800 |
commit | 6411defdcd6f560e74eaaaf3266f9efbb6dd81da (patch) | |
tree | f359e9537d6a34d436b6ffbb5aac6410bacd3af2 /src/intel/compiler/brw_reg.h | |
parent | 4e79a77cdc65af621f77c685b01cd18ace187965 (diff) |
intel/cs: Re-run final NIR optimizations for each SIMD size
With the advent of SPIR-V subgroup operations, compute shaders will have
to be slightly different depending on the SIMD size at which they
execute. In order to allow us to do dispatch-width specific things in
NIR, we re-run the final NIR stages for each sIMD width.
One side-effect of this change is that we start rallocing fs_visitors
which means we need DECLARE_RALLOC_CXX_OPERATORS.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_reg.h')
0 files changed, 0 insertions, 0 deletions