diff options
| author | Jason Ekstrand <[email protected]> | 2018-11-12 18:48:10 -0600 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2018-11-15 19:59:49 -0600 |
| commit | 6339aba775ecdcaf74136479d02e3622bc1d4c0a (patch) | |
| tree | bf3d0178ade3cccab3b89a19564a7418cc0dc070 /src/intel/compiler/brw_nir.c | |
| parent | d34fd81e7668b14158d63ade844a0e260b6f9152 (diff) | |
intel/compiler: Lower SSBO and shared loads/stores in NIR
We have a bunch of code to do this in the back-end compiler but it's
fairly specific to typed surface messages and the way we emit them.
This breaks it out into NIR were it's easier to do things a bit more
generally. It also means we can easily share the code between the vec4
and FS back-ends if we wish.
Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_nir.c')
| -rw-r--r-- | src/intel/compiler/brw_nir.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 10b03ef2fba..aa6788b9fe5 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -714,6 +714,8 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir) brw_nir_no_indirect_mask(compiler, nir->info.stage); OPT(nir_lower_indirect_derefs, indirect_mask); + OPT(brw_nir_lower_mem_access_bit_sizes); + /* Get rid of split copies */ nir = brw_nir_optimize(nir, compiler, is_scalar, false); |