diff options
| author | Jason Ekstrand <[email protected]> | 2019-02-08 17:51:24 -0600 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2019-03-04 23:56:39 +0000 |
| commit | 5c96120b5ce158fea28d751d8a55b5e4d80df4f3 (patch) | |
| tree | eef1bc4ec634ceb27c6691cc08737181580941f6 /src/intel/compiler/brw_nir.c | |
| parent | ca295ddbfb414a526d3bab7daf93fffbbc417c6e (diff) | |
intel,nir: Lower TXD with min_lod when the sampler index is not < 16
When we have a larger sampler index, we get into the "high sampler"
scenario and need an instruction header. Even in SIMD8, this pushes the
instruction over the sampler message size maximum of 11 registers.
Instead, we have to lower TXD to TXL.
Fixes: cb98e0755f8d "intel/fs: Support min_lod parameters on texture..."
Reviewed-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Ian Romanick <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_nir.c')
| -rw-r--r-- | src/intel/compiler/brw_nir.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 786f1298f22..07e9ccc8388 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -904,7 +904,9 @@ brw_nir_apply_sampler_key(nir_shader *nir, bool is_scalar) { const struct gen_device_info *devinfo = compiler->devinfo; - nir_lower_tex_options tex_options = { 0 }; + nir_lower_tex_options tex_options = { + .lower_txd_clamp_if_sampler_index_not_lt_16 = true, + }; /* Iron Lake and prior require lowering of all rectangle textures */ if (devinfo->gen < 6) |