diff options
author | Francisco Jerez <[email protected]> | 2018-02-24 16:05:21 -0800 |
---|---|---|
committer | Francisco Jerez <[email protected]> | 2018-03-02 11:28:56 -0800 |
commit | 4b4838b1ae46a0ce9fed88f275cc01167302cf24 (patch) | |
tree | 7c2feba5f25d0d122658ef01f2d362c42931c7b0 /src/intel/compiler/brw_fs_nir.cpp | |
parent | c063e88909e630bb4605037eb0fc072f40f8c2a2 (diff) |
Revert "i965/fs: Predicate byte scattered writes if needed"
This reverts commit a4031bdfa927fb4c3c5d0bdadc70634f3c1a5eac. It's
redundant with the sample mask predication done at this point by the
common logical send lowering infrastructure, and rather buggy because
it wasn't applying the correct sample mask in shaders using discard,
since the dispatch mask returned by FS_OPCODE_MOV_DISPATCH_TO_FLAGS
doesn't reflect samples discarded by the shader, so it could have led
to data corruption in fragment shader invocations that execute discard
based on a non-dynamically uniform condition.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_fs_nir.cpp')
-rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 15 |
1 files changed, 1 insertions, 14 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 47247875e8b..554d61d71af 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4207,25 +4207,12 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr * to rely on byte scattered in order to write 16-bit elements. * The byte_scattered_write message needs that every written 16-bit * type to be aligned 32-bits (stride=2). - * Additionally, while on Untyped Surface messages the - * bits of the execution mask are ANDed with the corresponding - * bits of the Pixel/Sample Mask, that is not the case for byte - * scattered writes. That is needed to avoid ssbo stores writing - * on helper invocations. So when that can affect, we load the - * sample mask, and predicate the send message. */ - brw_predicate pred = BRW_PREDICATE_NONE; - - if (stage == MESA_SHADER_FRAGMENT) { - bld.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS); - pred = BRW_PREDICATE_NORMAL; - } - emit_byte_scattered_write(bld, surf_index, offset_reg, write_src, 1 /* dims */, 1, bit_size, - pred); + BRW_PREDICATE_NONE); } else { assert(num_components * type_size <= 16); assert((num_components * type_size) % 4 == 0); |