diff options
| author | Jason Ekstrand <[email protected]> | 2019-09-01 22:12:07 -0500 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2019-09-06 03:58:09 +0000 |
| commit | d15fe8ca8262d502435c4f83985ac414f950bc5f (patch) | |
| tree | 06893693485af114474d618f898409fbaf01e332 /src/intel/compiler/brw_fs_nir.cpp | |
| parent | 47e974354715702a75ad2f1ee803b72cbd8cc9f1 (diff) | |
Revert "intel/fs: Move the scalar-region conversion to the generator."
This reverts commit c0504569eac5e5c305e9f0c240e248aca9d8891f. Now that
we're doing interpolation lowering in NIR, we can continue to stride the
FS input registers directly in the brw_fs_nir code like we did before.
This fixes SIMD32 fragment shaders which broke because lower_simd_width
depended on the 0 stride to split PLN instructions correctly.
Reviewed-by: Francisco Jerez <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_fs_nir.cpp')
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index f003abc2014..4e2881756ea 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -3632,8 +3632,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld, for (unsigned int i = 0; i < instr->num_components; i++) { fs_reg interp = - interp_reg(nir_intrinsic_base(instr), - nir_intrinsic_component(instr) + i); + component(interp_reg(nir_intrinsic_base(instr), + nir_intrinsic_component(instr) + i), 0); interp.type = BRW_REGISTER_TYPE_F; dest.type = BRW_REGISTER_TYPE_F; |