diff options
| author | Jason Ekstrand <[email protected]> | 2019-02-22 15:28:24 -0600 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2019-07-24 12:55:40 -0500 |
| commit | 4397eb91c1e0081be2b17edb13dd4b47b9e97b62 (patch) | |
| tree | 7d08bfc616373b6cddcce003852dcb86bc3ab4da /src/intel/compiler/brw_fs_nir.cpp | |
| parent | 799f0f7b28b90162a4c0a3e697c6d753e7528652 (diff) | |
intel/compiler: Allow for varying subgroup sizes
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_fs_nir.cpp')
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index e5a927431c4..6ea012c74b6 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4916,6 +4916,14 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr break; } + case nir_intrinsic_load_subgroup_size: + /* This should only happen for fragment shaders because every other case + * is lowered in NIR so we can optimize on it. + */ + assert(stage == MESA_SHADER_FRAGMENT); + bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), brw_imm_d(dispatch_width)); + break; + case nir_intrinsic_load_subgroup_invocation: bld.MOV(retype(dest, BRW_REGISTER_TYPE_D), nir_system_values[SYSTEM_VALUE_SUBGROUP_INVOCATION]); |