summaryrefslogtreecommitdiffstats
path: root/src/intel/compiler/brw_fs_nir.cpp
diff options
context:
space:
mode:
authorFrancisco Jerez <[email protected]>2016-04-25 17:29:57 -0700
committerJason Ekstrand <[email protected]>2018-06-28 13:19:38 -0700
commit1811cbdc25371362fcc7ab3dfe49bb020f7cc849 (patch)
tree5a480a4a4060f17e26c542dc274ca3f73757dce7 /src/intel/compiler/brw_fs_nir.cpp
parentd5b617a28e89fda62fb6cceec10686b0bb4b4fb2 (diff)
intel/fs: Disable SIMD32 dispatch on Gen4-6 with control flow
The hardware's control flow logic is 16-wide so we're out of luck here. We could, in theory, support SIMD32 if we know the control-flow is uniform but we don't have that information at this point. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_fs_nir.cpp')
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index e324519afc1..9273b300241 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -385,6 +385,10 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
nir_emit_cf_list(&if_stmt->else_list);
bld.emit(BRW_OPCODE_ENDIF);
+
+ if (devinfo->gen < 7)
+ limit_dispatch_width(16, "Non-uniform control flow unsupported "
+ "in SIMD32 mode.");
}
void
@@ -395,6 +399,10 @@ fs_visitor::nir_emit_loop(nir_loop *loop)
nir_emit_cf_list(&loop->body);
bld.emit(BRW_OPCODE_WHILE);
+
+ if (devinfo->gen < 7)
+ limit_dispatch_width(16, "Non-uniform control flow unsupported "
+ "in SIMD32 mode.");
}
void