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authorJason Ekstrand <[email protected]>2018-10-11 15:57:50 -0500
committerJason Ekstrand <[email protected]>2018-12-11 21:26:23 -0600
commitcb98e0755f8d05a5a7f9134e39c625e8933746ea (patch)
tree3a012b8beabe86ee713f00f3efdea7ae28fa0935 /src/intel/compiler/brw_fs_nir.cpp
parent4ef8f46fd12876146212e119c0e238c92796226a (diff)
intel/fs: Support min_lod parameters on texture instructions
We have to lower some shadow instructions because they don't exist in hardware and we have to lower txb+offset+clamp because the message gets too big and we run into the sampler message length limit of 11 regs. Acked-by: Ian Romanick <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_fs_nir.cpp')
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 165c70c7c29..d5a05aacdf5 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2968,7 +2968,7 @@ fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst,
/* Emit the instruction. */
const fs_reg srcs[] = { coords, fs_reg(), brw_imm_ud(0), fs_reg(),
- sample, mcs,
+ fs_reg(), sample, mcs,
brw_imm_ud(surface), brw_imm_ud(0),
fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
STATIC_ASSERT(ARRAY_SIZE(srcs) == TEX_LOGICAL_NUM_SRCS);
@@ -4792,6 +4792,10 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
break;
}
break;
+ case nir_tex_src_min_lod:
+ srcs[TEX_LOGICAL_SRC_MIN_LOD] =
+ retype(get_nir_src_imm(instr->src[i].src), BRW_REGISTER_TYPE_F);
+ break;
case nir_tex_src_ms_index:
srcs[TEX_LOGICAL_SRC_SAMPLE_INDEX] = retype(src, BRW_REGISTER_TYPE_UD);
break;