diff options
| author | Jason Ekstrand <[email protected]> | 2019-01-15 10:53:44 -0600 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2019-02-01 16:11:00 -0600 |
| commit | b4f0d062cd12b4f675bac900ac41d1085a79239a (patch) | |
| tree | c03f0758fe55af2a6c0ebefa937e27a7020e09c9 /src/intel/compiler/brw_fs_cse.cpp | |
| parent | 79724a07562dae79f00005b61bda4664287989ee (diff) | |
intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode
Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions. If you have a SIMD8 instruction in a SIMD16 shader,
neither would trigger and the restriction could still be hit.
Fixes: 232ed8980217dd "i965/fs: Register allocator shoudn't use grf127..."
Reviewed-by: Jose Maria Casanova Crespo <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_fs_cse.cpp')
0 files changed, 0 insertions, 0 deletions