diff options
author | Jason Ekstrand <[email protected]> | 2018-11-16 10:46:27 -0600 |
---|---|---|
committer | Jason Ekstrand <[email protected]> | 2019-01-29 18:43:55 +0000 |
commit | a920979d4f30a48a23f8ff375ce05fa8a947dd96 (patch) | |
tree | 3e5d67997b6b699c917395a80f6d2b4684e2314b /src/intel/compiler/brw_fs_builder.h | |
parent | 014edff0d20d52191570a4cb125c37b63955d664 (diff) |
intel/fs: Use split sends for surface writes on gen9+
Surface reads don't need them because they just have the one address
payload. With surface writes, on the other hand, we can put the address
and the data in the different halves and avoid building the payload all
together.
The decrease in register pressure and added freedom in register
allocation resulting from this change reduces spilling enough to improve
the performance of one customer benchmark by about 2x.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_fs_builder.h')
-rw-r--r-- | src/intel/compiler/brw_fs_builder.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index c50af4c1f55..3fc6e5f2c25 100644 --- a/src/intel/compiler/brw_fs_builder.h +++ b/src/intel/compiler/brw_fs_builder.h @@ -426,6 +426,21 @@ namespace brw { return src_reg(component(dst, 0)); } + src_reg + move_to_vgrf(const src_reg &src, unsigned num_components) const + { + src_reg *const src_comps = new src_reg[num_components]; + for (unsigned i = 0; i < num_components; i++) + src_comps[i] = offset(src, dispatch_width(), i); + + const dst_reg dst = vgrf(src.type, num_components); + LOAD_PAYLOAD(dst, src_comps, num_components, 0); + + delete[] src_comps; + + return src_reg(dst); + } + void emit_scan(enum opcode opcode, const dst_reg &tmp, unsigned cluster_size, brw_conditional_mod mod) const |