diff options
| author | Matt Turner <[email protected]> | 2017-06-14 11:03:19 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2018-02-28 11:15:47 -0800 |
| commit | 2cff3242109078999c57d5e6772418c09e835826 (patch) | |
| tree | 2a039fe05a88b4737fa7a88371a87eb5ec493bde /src/intel/compiler/brw_eu_validate.c | |
| parent | 58611ff913df74e7f790b0c572b983a992e25a17 (diff) | |
intel/compiler: Add Gen11+ native float type
This new type exposes the additional precision offered by the
accumulator register and will be used in the next patch to implement the
functionality of the PLN instruction using a pair of MAD instructions.
One weird thing to note: align1 ternary instructions may only have an
accumulator in the dst or src1 normally, but when src0's type is :NF
the accumulator is read.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_validate.c')
| -rw-r--r-- | src/intel/compiler/brw_eu_validate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index 6ee6b4ffbe7..d3189d1ef5e 100644 --- a/src/intel/compiler/brw_eu_validate.c +++ b/src/intel/compiler/brw_eu_validate.c @@ -277,6 +277,7 @@ static enum brw_reg_type execution_type_for_type(enum brw_reg_type type) { switch (type) { + case BRW_REGISTER_TYPE_NF: case BRW_REGISTER_TYPE_DF: case BRW_REGISTER_TYPE_F: case BRW_REGISTER_TYPE_HF: |