diff options
author | Jose Maria Casanova Crespo <[email protected]> | 2017-07-01 08:16:01 +0200 |
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committer | Jose Maria Casanova Crespo <[email protected]> | 2017-12-06 08:57:18 +0100 |
commit | f1a9936ee1c7d2abe641eb785786c908c5ed799c (patch) | |
tree | a7a59655005f2c8d5d19c38dbf14e22a5174af02 /src/intel/compiler/brw_eu_emit.c | |
parent | d038deaa400c819e5867d1e417849b124ccd07b3 (diff) |
i965/fs: Add byte scattered write message and fs support
v2: (Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_write.
v3: - Remove leftover newline (Topi Pohjolainen)
- Rename brw_data_size to brw_scattered_data_element and use
defines instead of an enum (Jason Ekstrand)
- Assert scattered write for Gen8+ and Haswell (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <[email protected]>
Signed-off-by: Alejandro PiƱeiro <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_emit.c')
-rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index ca97ff7325e..bf9d3c945a9 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -2983,6 +2983,50 @@ brw_untyped_surface_write(struct brw_codegen *p, p, insn, num_channels); } +static unsigned +brw_byte_scattered_data_element_from_bit_size(unsigned bit_size) +{ + switch (bit_size) { + case 8: + return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE; + case 16: + return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD; + case 32: + return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD; + default: + unreachable("Unsupported bit_size for byte scattered messages"); + } +} + +void +brw_byte_scattered_write(struct brw_codegen *p, + struct brw_reg payload, + struct brw_reg surface, + unsigned msg_length, + unsigned bit_size) +{ + const struct gen_device_info *devinfo = p->devinfo; + assert(devinfo->gen > 7 || devinfo->is_haswell); + assert(brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1); + const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE; + + struct brw_inst *insn = brw_send_indirect_surface_message( + p, sfid, brw_writemask(brw_null_reg(), WRITEMASK_XYZW), + payload, surface, msg_length, 0, true); + + unsigned msg_control = + brw_byte_scattered_data_element_from_bit_size(bit_size) << 2; + + if (brw_inst_exec_size(devinfo, p->current) == BRW_EXECUTE_16) + msg_control |= 1; + else + msg_control |= 0; + + brw_inst_set_dp_msg_type(devinfo, insn, + HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE); + brw_inst_set_dp_msg_control(devinfo, insn, msg_control); +} + static void brw_set_dp_typed_atomic_message(struct brw_codegen *p, struct brw_inst *insn, |