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authorFrancisco Jerez <[email protected]>2018-01-23 19:23:20 -0800
committerFrancisco Jerez <[email protected]>2019-10-11 12:24:16 -0700
commit057902dcf8d287f0b110b03f67ae33d338a7497c (patch)
tree0d7666abc6739224fecac2154d98833ff1bb44b5 /src/intel/compiler/brw_eu_emit.c
parent25dd67099df301f09ce40b8f9c5a3bbc857e367c (diff)
intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.
Change brw_inst_set_opcode() and brw_inst_opcode() to call brw_opcode_encode/decode() transparently in order to translate between hardware and IR opcodes, and update the EU compaction code in order to do the same as needed, so we can eventually drop the one-to-one correspondence between hardware and IR opcodes. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_emit.c')
-rw-r--r--src/intel/compiler/brw_eu_emit.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index c6b6561ee7b..609edaffdc3 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2740,6 +2740,8 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset)
case BRW_OPCODE_HALT:
if (depth == 0)
return offset;
+ default:
+ break;
}
}
@@ -2845,6 +2847,9 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset)
assert(brw_inst_uip(devinfo, insn) != 0);
assert(brw_inst_jip(devinfo, insn) != 0);
break;
+
+ default:
+ break;
}
}
}