diff options
| author | Matt Turner <[email protected]> | 2017-06-14 14:47:19 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2018-02-28 11:15:47 -0800 |
| commit | 432674ce93ceee2abd7e0cc4171bc36a499d4c1f (patch) | |
| tree | 997367c0830f7f3651ddb865d82035ba822eb7da /src/intel/compiler/brw_eu_emit.c | |
| parent | b5d8781e19559a8f9850f1a900ef93ffa3617faa (diff) | |
intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+
The PLN instruction is no more. Its functionality is now implemented
using two MAD instructions with the new native-float type. Instead of
pln(16) r20.0<1>:F r10.4<0;1,0>:F r4.0<8;8,1>:F
we now have
mad(8) acc0<1>:NF r10.7<0;1,0>:F r4.0<8;8,1>:F r10.4<0;1,0>:F
mad(8) r20.0<1>:F acc0<8;8,1>:NF r5.0<8;8,1>:F r10.5<0;1,0>:F
mad(8) acc0<1>:NF r10.7<0;1,0>:F r6.0<8;8,1>:F r10.4<0;1,0>:F
mad(8) r21.0<1>:F acc0<8;8,1>:NF r7.0<8;8,1>:F r10.5<0;1,0>:F
... and in the case of SIMD8 only the first pair of MAD instructions is
used.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_emit.c')
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index ec871e5aa75..a96fe43556e 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -968,7 +968,7 @@ ALU2(DP4) ALU2(DPH) ALU2(DP3) ALU2(DP2) -ALU3F(MAD) +ALU3(MAD) ALU3F(LRP) ALU1(BFREV) ALU3(BFE) |