diff options
| author | Matt Turner <[email protected]> | 2017-07-25 13:16:25 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2017-08-21 14:05:23 -0700 |
| commit | 8815b9677ff70723ee55f2e567d50c1d4e9762b3 (patch) | |
| tree | 1f35a3b1b8323be588a5893a71d85d1339bd88a9 /src/intel/compiler/brw_eu_emit.c | |
| parent | ce6b8627d87f14e15f2f4bbc6034b32c34557cb3 (diff) | |
i965: Reorder brw_reg_type enum values
These vaguely corresponded to the hardware encodings, but that is purely
historical at this point. Reorder them so we stop making things "almost
work" when mixing enums.
The ordering has been closen so that no enum value is the same as a
compatible hardware encoding.
Reviewed-by: Scott D Phillips <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_emit.c')
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 6673e0741a8..b59fc33a547 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -112,7 +112,6 @@ brw_reg_type_to_hw_type(const struct gen_device_info *devinfo, }; assert(type < ARRAY_SIZE(imm_hw_types)); assert(imm_hw_types[type] != -1); - assert(devinfo->gen >= 8 || type < BRW_REGISTER_TYPE_DF); return imm_hw_types[type]; } else { /* Non-immediate registers */ @@ -134,8 +133,6 @@ brw_reg_type_to_hw_type(const struct gen_device_info *devinfo, }; assert(type < ARRAY_SIZE(hw_types)); assert(hw_types[type] != -1); - assert(devinfo->gen >= 7 || type < BRW_REGISTER_TYPE_DF); - assert(devinfo->gen >= 8 || type < BRW_REGISTER_TYPE_Q); return hw_types[type]; } } @@ -184,9 +181,6 @@ brw_hw_reg_type_to_size(const struct gen_device_info *devinfo, [GEN8_HW_REG_NON_IMM_TYPE_HF] = 2, }; assert(type < ARRAY_SIZE(hw_sizes)); - assert(devinfo->gen >= 7 || - (type < GEN7_HW_REG_NON_IMM_TYPE_DF || type == BRW_HW_REG_TYPE_F)); - assert(devinfo->gen >= 8 || type <= BRW_HW_REG_TYPE_F); return hw_sizes[type]; } } |