diff options
| author | Sagar Ghuge <[email protected]> | 2019-05-29 11:43:30 -0700 |
|---|---|---|
| committer | Sagar Ghuge <[email protected]> | 2019-07-01 10:14:22 -0700 |
| commit | 83fdec0f0deb98a7f48186679a491f3128fdd1fe (patch) | |
| tree | cfda74c5ed1cc80dc029c0706cb17d705c54932a /src/intel/compiler/brw_eu_emit.c | |
| parent | 8d74749f812e64968d37266061293e204fea252c (diff) | |
intel/compiler: Enable the emission of ROR/ROL instructions
v2: 1) Drop changes for vec4 backend as on Gen11+ we don't support
align16 mode (Matt Turner)
Signed-off-by: Sagar Ghuge <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_emit.c')
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 6cb4f7bdbf1..8e7263ce447 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -981,6 +981,8 @@ ALU2(SHR) ALU2(SHL) ALU1(DIM) ALU2(ASR) +ALU2(ROL) +ALU2(ROR) ALU3(CSEL) ALU1(FRC) ALU1(RNDD) |