diff options
| author | Kenneth Graunke <[email protected]> | 2015-11-22 20:12:17 -0800 |
|---|---|---|
| committer | Ian Romanick <[email protected]> | 2018-03-08 15:26:26 -0800 |
| commit | 70de61594dcf99f24eb31ebf98d62f13e1f44c2e (patch) | |
| tree | a745f0a99d5626cad6545a0c2598c0d825ff608f /src/intel/compiler/brw_eu_emit.c | |
| parent | 54e8d2268de37f320b2d206295d0b519f5be5ab7 (diff) | |
i965/fs: Add infrastructure for generating CSEL instructions.
v2 (idr): Don't allow CSEL with a non-float src2.
v3 (idr): Add CSEL to fs_inst::flags_written. Suggested by Matt.
v4 (idr): Only set BRW_ALIGN_16 on Gen < 10 (suggested by Matt). Don't
reset the access mode afterwards (suggested by Samuel and Matt). Add
support for CSEL not modifying the flags to more places (requested by
Matt).
Signed-off-by: Kenneth Graunke <[email protected]>
Signed-off-by: Ian Romanick <[email protected]>
Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> [v3]
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_emit.c')
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index f8102e014e5..f039af56d05 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -959,6 +959,7 @@ ALU2(SHR) ALU2(SHL) ALU1(DIM) ALU2(ASR) +ALU3(CSEL) ALU1(FRC) ALU1(RNDD) ALU2(MAC) |