diff options
| author | Jason Ekstrand <[email protected]> | 2017-09-01 15:18:02 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2018-03-07 12:13:47 -0800 |
| commit | 8b4a5e641bc3cb9cf0cfe7d0487926127fc25de7 (patch) | |
| tree | 677f320e6c04883a55a4f2592549428154972423 /src/intel/compiler/brw_eu_defines.h | |
| parent | 2292b20b2969c9e3e0494ccc55c6216f330762ae (diff) | |
intel/fs: Add support for subgroup quad operations
NIR has code to lower these away for us but we can do significantly
better in many cases with register regioning and SIMD4x2.
Acked-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_defines.h')
| -rw-r--r-- | src/intel/compiler/brw_eu_defines.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 3c4c538ac17..332d627bc37 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -467,6 +467,11 @@ enum opcode { */ SHADER_OPCODE_SEL_EXEC, + /* This turns into an align16 mov from src0 to dst with a swizzle + * provided as an immediate in src1. + */ + SHADER_OPCODE_QUAD_SWIZZLE, + /* Take every Nth element in src0 and broadcast it to the group of N * channels in which it lives in the destination. The offset within the * cluster is given by src1 and the cluster size is given by src2. |