diff options
| author | Jose Maria Casanova Crespo <[email protected]> | 2017-07-01 08:19:17 +0200 |
|---|---|---|
| committer | Jose Maria Casanova Crespo <[email protected]> | 2017-12-06 08:57:18 +0100 |
| commit | c57a3f200dd50e345a9983e5ae950091e6241af6 (patch) | |
| tree | 2355bd52109784482d26aebf16cdf7129505c650 /src/intel/compiler/brw_eu.h | |
| parent | a4031bdfa927fb4c3c5d0bdadc70634f3c1a5eac (diff) | |
i965/fs: Add byte scattered read message and fs support
v2: Fix alignment style (Topi Pohjolainen)
(Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_read.
v3: (Jason Ekstrand)
- Use renamed brw_byte_scattered_data_element_from_bit_size method
- Assert scattered read for Gen8+ and Haswell.
- Use conditional expresion at components_read.
- Include comment about params for scattered opcodes.
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu.h')
| -rw-r--r-- | src/intel/compiler/brw_eu.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index 3ac3b4342a9..2d0f56f7938 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -486,6 +486,14 @@ brw_typed_surface_write(struct brw_codegen *p, unsigned num_channels); void +brw_byte_scattered_read(struct brw_codegen *p, + struct brw_reg dst, + struct brw_reg payload, + struct brw_reg surface, + unsigned msg_length, + unsigned bit_size); + +void brw_byte_scattered_write(struct brw_codegen *p, struct brw_reg payload, struct brw_reg surface, |