diff options
| author | Sagar Ghuge <[email protected]> | 2019-05-29 11:43:30 -0700 |
|---|---|---|
| committer | Sagar Ghuge <[email protected]> | 2019-07-01 10:14:22 -0700 |
| commit | 83fdec0f0deb98a7f48186679a491f3128fdd1fe (patch) | |
| tree | cfda74c5ed1cc80dc029c0706cb17d705c54932a /src/intel/compiler/brw_eu.c | |
| parent | 8d74749f812e64968d37266061293e204fea252c (diff) | |
intel/compiler: Enable the emission of ROR/ROL instructions
v2: 1) Drop changes for vec4 backend as on Gen11+ we don't support
align16 mode (Matt Turner)
Signed-off-by: Sagar Ghuge <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu.c')
| -rw-r--r-- | src/intel/compiler/brw_eu.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c index 87a6145ac29..ec30579446b 100644 --- a/src/intel/compiler/brw_eu.c +++ b/src/intel/compiler/brw_eu.c @@ -488,7 +488,13 @@ static const struct opcode_desc opcode_descs[128] = { [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, - /* Reserved - 13-15 */ + /* Reserved - 13 */ + [BRW_OPCODE_ROR] = { + .name = "ror", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN11), + }, + [BRW_OPCODE_ROL] = { + .name = "rol", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN11), + }, [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, |