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authorSagar Ghuge <[email protected]>2019-03-23 20:02:54 -0700
committerMatt Turner <[email protected]>2019-05-07 14:33:48 -0700
commit5211159b5b469409ac9c6d8b52535c5bb544c508 (patch)
tree91205b1e79cd1a9b22e6b5b71fa2cfd9a51e572b /src/intel/compiler/brw_disasm.c
parent4e828bb48abf12d43c2b4a373b4b2125c90ea152 (diff)
intel/compiler: Print quad value in hex format
Print quad value same as unsigned quad so that we can distinguish in between quater control disassembled values for e.g 1/2/3[Q] and immediate quad value for e.g 1Q. This allows round-tripping through the assembler/disassembler. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_disasm.c')
-rw-r--r--src/intel/compiler/brw_disasm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index efca3e2ce7d..04efa965cef 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1309,7 +1309,7 @@ imm(FILE *file, const struct gen_device_info *devinfo, enum brw_reg_type type,
format(file, "0x%016"PRIx64"UQ", brw_inst_imm_uq(devinfo, inst));
break;
case BRW_REGISTER_TYPE_Q:
- format(file, "%"PRId64"Q", brw_inst_imm_uq(devinfo, inst));
+ format(file, "0x%016"PRIx64"Q", brw_inst_imm_uq(devinfo, inst));
break;
case BRW_REGISTER_TYPE_UD:
format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst));