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authorJason Ekstrand <[email protected]>2018-05-25 22:23:30 -0700
committerJason Ekstrand <[email protected]>2018-06-28 13:19:38 -0700
commitdb6ca13efc1b14ee7a8d563f23c937a9a86ef569 (patch)
tree0dbbcce57c3886b1ba453aad8b69224a724c5f80 /src/intel/compiler/brw_compiler.h
parent566e6abd6d70266aea2f43ad9fefaf7718d76c57 (diff)
intel/fs: Emit LINE+MAC for LINTERP with unaligned coordinates
On g4x through Sandy Bridge, src1 (the coordinates) of the PLN instruction is required to be an even register number. When it's odd (which can happen with SIMD32), we have to emit a LINE+MAC combination instead. Unfortunately, we can't just fall through to the gen4 case because the input registers are still set up for PLN which lays out the four src1 registers differently in SIMD16 than LINE. v2 (Jason Ekstrand): - Take advantage of both accumulators and emit LINE LINE MAC MAC (Based on a patch from Francisco Jerez) - Unify the gen4 and gen4x-6 cases using a loop v3 (Jason Ekstrand): - Don't unify gen4 with gen4x-6 as this turns out to be more fragile than first thought without reworking the gen4 barycentric coordinate layout. Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_compiler.h')
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