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authorFrancisco Jerez <[email protected]>2017-04-09 17:28:58 -0700
committerFrancisco Jerez <[email protected]>2017-04-11 15:28:54 -0700
commit147e71242ce539ff28e282f009c332818c35f5ac (patch)
tree8a6e8d5472dcf8827f5d38e1bfc7eb6d774b0889 /src/intel/compiler/brw_cfg.h
parent9a7b257450fdcb8ae2c998caf24af040722a541a (diff)
i965/fs: Take into account lower frequency of conditional blocks in spilling cost heuristic.
The individual branches of an if/else/endif construct will be executed some unknown number of times between 0 and 1 relative to the parent block. Use some factor in between as weight while approximating the cost of spill/fill instructions within a conditional if-else branch. This favors spilling registers used within conditional branches which are likely to be executed less frequently than registers used at the top level. Improves the framerate of the SynMark2 OglCSDof benchmark by ~1.9x on my SKL GT4e. Should have a comparable effect on other platforms. No significant regressions. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
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