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authorRafael Antognolli <[email protected]>2019-07-19 15:30:56 -0700
committerRafael Antognolli <[email protected]>2019-08-12 16:19:08 -0700
commit32344dc5811021409f04db50f461582c05aa6a80 (patch)
treedbfefb59e26ae878eabf6f03f418cd7739f9b258 /src/intel/common
parente1cb71c18213bbe50983b6edeac061df89bef718 (diff)
intel/gen_decoder: Decode SLICE_HASH_TABLE.
Diffstat (limited to 'src/intel/common')
-rw-r--r--src/intel/common/gen_batch_decoder.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/common/gen_batch_decoder.c b/src/intel/common/gen_batch_decoder.c
index e44c352a053..5dc38c86ef3 100644
--- a/src/intel/common/gen_batch_decoder.c
+++ b/src/intel/common/gen_batch_decoder.c
@@ -753,6 +753,13 @@ decode_3dstate_scissor_state_pointers(struct gen_batch_decode_ctx *ctx,
}
static void
+decode_3dstate_slice_table_state_pointers(struct gen_batch_decode_ctx *ctx,
+ const uint32_t *p)
+{
+ decode_dynamic_state_pointers(ctx, "SLICE_HASH_TABLE", p, 1);
+}
+
+static void
decode_load_register_imm(struct gen_batch_decode_ctx *ctx, const uint32_t *p)
{
struct gen_group *reg = gen_spec_find_register(ctx->spec, p[1]);
@@ -801,6 +808,7 @@ struct custom_decoder {
{ "3DSTATE_BLEND_STATE_POINTERS", decode_3dstate_blend_state_pointers },
{ "3DSTATE_CC_STATE_POINTERS", decode_3dstate_cc_state_pointers },
{ "3DSTATE_SCISSOR_STATE_POINTERS", decode_3dstate_scissor_state_pointers },
+ { "3DSTATE_SLICE_TABLE_STATE_POINTERS", decode_3dstate_slice_table_state_pointers },
{ "MI_LOAD_REGISTER_IMM", decode_load_register_imm }
};