diff options
| author | Nanley Chery <[email protected]> | 2019-08-08 13:40:08 -0700 |
|---|---|---|
| committer | Nanley Chery <[email protected]> | 2019-10-28 10:47:05 -0700 |
| commit | 6670e07a6efb69951c45583b51d51de31c9e7119 (patch) | |
| tree | 111b955273d57ecce57ec658d1498c05bfaa0ab9 /src/intel/common | |
| parent | f93bc14618ae22a3d3b8030be6ba58d589f0bab8 (diff) | |
intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+
While this format isn't listed in BSpec: 53911, other documentation and
empirical evidence suggest that it's fine to remap it to R32_FLOAT. I've
filed a bug for the BSpec page.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/common')
| -rw-r--r-- | src/intel/common/gen_aux_map.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/common/gen_aux_map.c b/src/intel/common/gen_aux_map.c index 7acf03cbb2e..398f02416db 100644 --- a/src/intel/common/gen_aux_map.c +++ b/src/intel/common/gen_aux_map.c @@ -321,6 +321,7 @@ get_format_encoding(const struct isl_surf *isl_surf) case ISL_FORMAT_R32_SINT: return 0x12; case ISL_FORMAT_R32_UINT: return 0x13; case ISL_FORMAT_R32_FLOAT: return 0x11; + case ISL_FORMAT_R24_UNORM_X8_TYPELESS: return 0x11; case ISL_FORMAT_B5G6R5_UNORM: return 0xA; case ISL_FORMAT_B5G6R5_UNORM_SRGB: return 0xA; case ISL_FORMAT_B5G5R5A1_UNORM: return 0xA; |